VLSI: April 2010

LSI LOGIC -LSI Corporation is a leading provider of innovative silicon, systems and software technologies that enable products which seamlessly bring people, information and digital content together. Th a broad portfolio of capabilities and services including custom and standard product ICs, adapters, systems and software that are trusted by the world's best known brands to power leading solutions in the storage and networking markets. (www.lsi.com)

eInfoChips eInfochips is a technology design services & solutions company offering IPs & services in Software Products & Applications, Embedded System and ASIC/FPGA since 1994.(www.einfochips.com)

ConexantConexant Systems, Inc. (NASDAQ: CNXT) is a leading provider of solutions for imaging, audio, embedded modem, and video surveillance applications – areas where the company has established leadership positions. (www.conexant.co.in)

Sasken
With over 1500+ man years of experience in the VLSI space, Sasken delivers ASIC services and FPGA services to it’s customers in the Wireless, Communications, Consumer, Automotive, Networking & Defense domains.

http://www.sasken.com/services/ASIC_design_services.html

Tensilica (www.tensilica.com)
Tensilica is a fast growing, pre-IPO, venture-backed company focused on providing the ultimate in application specific microprocessor solutions for use in today's high volume embedded systems. .http://www.tensilica.com/company/careers.htm

nVidia I dont know whether any VLSI design goes there,You can go through following links (www.nvidia.co.in/page/home.html).

(www.nvidia.in/object/india_pune.html).

Wipro I dont got much info about this in VLSI..(www.wipro.com).

The MOSFET can be used as a switch as in figure show.Under the normal DC conditions ,the gate of MOSFET doesn't draws the current.Figure two shows the small signal resistance of the switches. So the Transmission gates are good as switch because at both conditions they provide strong VDD because of PMOS and strong zero because of NMOS {about strong zero and stron 1,refer link1}.

Limitations:
1)Charge Injection2)Clock(or capacitive) feed-through.
3)KT/C noise

We will see each of then in slight details
1)Charge Injection:The figure below shows the typical NMOS charge injection.When MOSFET is on ,due to small VDS there is small charge Q'c at the channel ..So when the MOS goes off ,the charge is distributed on both sides through source and drain i.e. towards the capacitor and tto the Vin ,but as all Vin source has low impedence the charge has no effect on Vin but it changes the voltage across CLoad .
There are lot many researches going on ,it is seen that if clock is very fast (turns off fast) the charge is equally distributed on both sides of the MOS. So we get 50% at C load side.
if clock makes slow transition all the charge could be absorbed at input.

We have Q=CV ,The total charge across the channel is given by Qch = WL*Cox(Vgs -Vth).
Where WL is the area of the channel.

Characterizing charge Injection
Change in the voltage across the load (if NMOS) is given by

Where Vdd-Vin =Vgs, Cox is the gate capacitance per unit area . Divide by 2 because 50 %.So in above euation ,you can see that the change in voltage across Cload is nonlinear with respect to Vin due to the threshold voltage.

In sampled-data systems, charge injection will result in non-linearity errors. So it should be obvious here that charge injection effects should be minimized as much as possible.

The sampled output is given by Vout=Vin-Delta(Vout).
The error for the NMOS switch appears as a "negative pedestal" at the output..

I am slight Busy ...have LOt in my mind but not the time to upload ,put jpeg files ..etc ...I will put everythin one by one in detail soon

VLSI

Monday, April 26, 2010

VLSI COMPANIES

Wednesday, April 21, 2010

MOSFET as Switch

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